- pipeline stall
- 1) остановка конвейера2) вчт сбой последовательности выполнения команд с конвейерной передачей данных, проф. остановка конвейера
English-Russian electronics dictionary .
pipeline stall
Смотреть что такое "pipeline stall" в других словарях:
pipeline stall — A microprocessor design error that leads to delays in the processing of an instruction … Dictionary of networking
Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… … Wikipedia
List of pipeline accidents — The following is a list of pipeline accidents: This is an incomplete list, which may never be able to satisfy particular standards for completeness. You can help by expanding it with reliably sourced entries. Contents 1 Bel … Wikipedia
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Compiler optimization — is the process of tuning the output of a compiler to minimize or maximize some attributes of an executable computer program. The most common requirement is to minimize the time taken to execute a program; a less common one is to minimize the… … Wikipedia
Hazard (computer architecture) — Hazards are problems with the instruction pipeline in central processing unit (CPU) microarchitectures that potentially result in incorrect computation. There are typically three types of hazards: data hazards structural hazards control hazards… … Wikipedia
Instruction scheduling — In computer science, instruction scheduling is a compiler optimization used to improve instruction level parallelism, which improves performance on machines with instruction pipelines. Put more simply, without changing the meaning of the code, it … Wikipedia
Barrel processor — A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as interleaved or fine grained temporal multithreading. As opposed to simultaneous multithreading in modern superscalar … Wikipedia
Язык ассемблера — Листинг программы на языке ассемблера Motorola MC6800 (слева идут адреса и машинные коды в шестнадцатеричной системе, вычисленные и сгенерированн … Википедия
Loop inversion — is a compiler optimization, a loop transformation, which replaces a while loop by an if block containing a do..while loop. Example in C int i, a [100] ; i = 0; while (i < 100) { a [i] = 0; i++; }is equivalent to: int i, a [100] ; i = 0; if (i … Wikipedia
Loop optimization — In compiler theory, loop optimization plays an important role in improving cache performance, making effective use of parallel processing capabilities, and reducing overheads associated with executing loops. Most execution time of a scientific… … Wikipedia
